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general description the max7030 crystal-based, fractional-n transceiver is designed to transmit and receive ask/ook data at fac- tory-preset carrier frequencies of 315mhz or 433.92mhz with data rates up to 33kbps (manchester encoded) or 66kbps (nrz encoded). this device gen- erates a typical output power of +10dbm into a 50 load and exhibits typical sensitivity of -114dbm. the max7030 features separate transmit and receive pins (paout and lnain) and provides an internal rf switch that can be used to connect the transmit and receive pins to a common antenna. the max7030 transmit frequency is generated by a 16- bit, fractional-n, phase-locked loop (pll), while the receiver? local oscillator (lo) is generated by an inte- ger-n pll. this hybrid architecture eliminates the need for separate transmit and receive crystal reference oscillators because the fractional-n pll is preset to be 10.7mhz above the receive lo. retaining the fixed-n pll for the receiver avoids the higher current-drain requirements of a fractional-n pll and keeps the receiver current drain as low as possible. all frequency- generation components are integrated on-chip, and only a crystal, a 10.7mhz if filter, and a few discrete components are required to implement a complete antenna/digital data solution. the max7030 is available in a small, 5mm x 5mm, 32- pin thin qfn package, and is specified to operate over the automotive -40? to +125? temperature range. applications 2-way remote keyless entry security systems home automation remote controls remote sensing smoke alarms garage door openers local telemetry systems features ? +2.1v to +3.6v or +4.5v to +5.5v single-supply operation ? single-crystal transceiver ? factory-preset frequency (no serial interface required) ? ask/ook modulation ? +10dbm output power into 50 load ? integrated tx/rx switch ? integrated transmit and receive pll, vco, and loop filter ? > 45db image rejection ? typical rf sensitivity*: -114dbm ? selectable if bandwidth with external filter ? < 12.5ma transmit-mode current ? < 6.7ma receive-mode current ? < 800na shutdown current ? fast-on startup feature, < 250 s ? small, 32-pin, thin qfn package max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll ordering information 19-3706; rev 4; 6/12 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max7030_atj+ -40 c to +125 c 32 thin qfn-ep** product selector guide part carrier frequency (mhz) max7030latj+ 315 max7030hatj+ 433.92 * 0.2% ber, 4kbps manchester-encoded data, 280khz if bw + denotes a lead(pb)-free/rohs-compliant package. ** ep = exposed pad. note: the max7030 is available with factory-preset operating frequencies. see the product selector guide for complete part numbers. pin configuration, typical application circuit, and functional diagram appear at end of data sheet.
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 2 absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. hvin to gnd .........................................................-0.3v to +6.0v pavdd, avdd, dvdd to gnd..............................-0.3v to +4.0v enable, t/ r , data, agc0, agc1, agc2 to gnd .......................................-0.3v to (v hvin + 0.3v) all other pins to gnd .............................-0.3v to (v _vdd + 0.3v) continuous power dissipation (t a = +70?) 32-pin thin qfn (derate 21.3mw/? above +70?).............................................................1702mw operating temperature range .........................-40? to +125? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? dc electrical characteristics ( typical application circuit , 50 system impedance, v avdd = v dvdd = v hvin = v pavdd = +2.1v to +3.6v, f rf = 315mhz or 433.92mhz, t a = -40? to +125?, unless otherwise noted. typical values are at v avdd = v dvdd = v hvin = v pavdd = +2.7v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units supply voltage (3v mode) v dd hvin, pavdd, avdd, and dvdd connected to power supply 2.1 2.7 3.6 v supply voltage (5v mode) hvin pavdd, avdd, and dvdd unconnected from hvin, but connected together 4.5 5.0 5.5 v f rf = 315mhz 3.5 5.4 transmit mode, pa off, v data at 0% duty cycle (note 2) f rf = 434mhz 4.3 6.7 f rf = 315mhz 7.6 12.3 transmit mode, v data at 50% duty cycle (notes 3, 4) f rf = 434mhz 8.4 13.6 f rf = 315mhz 11.6 19.1 transmit mode, v data at 100% duty cycle (note 2) f rf = 434mhz 12.4 20.4 receiver 315mhz 6.1 7.9 receiver 434mhz 6.4 8.3 ma deep-sleep (3v mode) 0.8 8.8 t a < +85?, typ at +25? (note 4) deep-sleep (5v mode) 2.4 10.9 ? receiver 315mhz 6.4 8.2 receiver 434mhz 6.7 8.4 ma deep-sleep (3v mode) 8.0 34.2 supply current i dd t a < +125?, typ at +125? (note 2) deep-sleep (5v mode) 14.9 39.3 ? voltage regulator v reg v hvin = 5v, i load = 15ma 3.0 v digital i/o input-high threshold v ih (note 2) 0.9 x v hvin v input-low threshold v il (note 2) 0.1 x v hvin v
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 3 ac electrical characteristics ( typical application circuit , 50 system impedance, v pavdd = v avdd = v dvdd = v hvin = +2.1v to +3.6v, f rf = 315mhz or 433.92mhz, t a = -40? to +125?, unless otherwise noted. typical values are at v pavdd = v avdd = v dvdd = v hvin = +2.7v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units general characteristics frequency range 315/433.92 mhz maximum input level p rfin 0 dbm f rf = 315mhz (note 6) 32 transmit efficiency 100% duty cycle f rf = 434mhz (note 6) 30 % f rf = 315mhz (note 6) 24 transmit efficiency 50% duty cycle f rf = 434mhz (note 6) 22 % enable or t/ r transition low to high, transmitter frequency settled to within 50khz of the desired carrier 200 enable or t/ r transition low to high, transmitter frequency settled to within 5khz of the desired carrier 350 power-on time t on enable transition low to high, or t/ r transition high to low, receiver startup time (note 5) 250 s receiver 315mh z -114 sensitivity 0.2% ber, 4kbps manchester data rate, 280khz if bw, average rf power 434mh z -113 dbm image rejection 46 db power amplifier t a = +25 c (note 4) 4.6 10.0 15.5 t a = +125 c, v pavdd = v avdd = v dvdd = v hvin = +2.1v (note 2) 3.9 6.7 output power p out t a = -40 c, v pavdd = v avdd = v dvdd = v hvin = +3.6v (note 4) 13.1 15.8 dbm modulation depth 82 db maximum carrier harmonics with output-matching network -40 dbc reference spur -50 dbc dc electrical characteristics (continued) ( typical application circuit , 50 system impedance, v avdd = v dvdd = v hvin = v pavdd = +2.1v to +3.6v, f rf = 315mhz or 433.92mhz, t a = -40? to +125?, unless otherwise noted. typical values are at v avdd = v dvdd = v hvin = v pavdd = +2.7v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units pulldown sink current agc 0- 2, e n able , t/ r , d ata ( v h v i n = 5.5v ) 20 ? output-low voltage v ol i sink = 500? 0.15 v output-high voltage v oh i source = 500? v h v in - 0.26 v
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 4 ac electrical characteristics (continued) ( typical application circuit , 50 system impedance, v pavdd = v avdd = v dvdd = v hvin = +2.1v to +3.6v, f rf = 315mhz or 433.92mhz, t a = -40? to +125?, unless otherwise noted. typical values are at v pavdd = v avdd = v dvdd = v hvin = +2.7v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units phase-locked loop transmit vco gain k vco 340 mhz/v 10khz offset, 200khz loop bw -68 transmit pll phase noise 1mhz offset, 200khz loop bw -98 dbc/hz receive vco gain 340 mhz/v 10khz offset, 500khz loop bw -80 receive pll phase noise 1mhz offset, 500khz loop bw -90 dbc/hz transmit pll 200 loop bandwidth receive pll 500 khz reference frequency input level 0.5 v p-p low-noise amplifier/mixer (note 8) f rf = 315mhz 1 - j4.7 lna input impedance z inlna normalized to 50 f rf = 434mhz 1- j3.3 f rf = 315mhz 50 high-gain state f rf = 434mhz 45 f rf = 315mhz 13 voltage-conversion gain low-gain state f rf = 434mhz 9 db high-gain state -42 input-referred, 3rd-order intercept point iip3 low-gain state -6 dbm mixer-output impedance 330 lo signal feedthrough to antenna -100 dbm rssi input impedance 330 operating frequency f if 10.7 mhz 3db bandwidth 10 mhz gain 15 mv/db analog baseband maximum data-filter bandwidth 50 khz maximum data-slicer bandwidth 100 khz maximum peak-detector bandwidth 50 khz manchester coded 33 maximum data rate nonreturn to zero (nrz) 66 kbps
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 5 ac electrical characteristics (continued) ( typical application circuit , 50 system impedance, v pavdd = v avdd = v dvdd = v hvin = +2.1v to +3.6v, f rf = 315mhz or 433.92mhz, t a = -40? to +125?, unless otherwise noted. typical values are at v pavdd = v avdd = v dvdd = v hvin = +2.7v, t a = +25?, unless otherwise noted.) (note 1) note 1: supply current, output power, and efficiency are greatly dependent on board layout and paout match. note 2: 100% tested at t a = +125?. guaranteed by design and characterization overtemperature. note 3: 50% duty cycle at 10khz ask data (manchester coded). note 4: guaranteed by design and characterization. not production tested. note 5: time for final signal detection; does not include baseband filter settling. note 6: efficiency = p out /(v dd x i dd ). note 7: dependent on pcb trace capacitance. note 8: input impedance is measured at the lnain pin. note that the impedance at 315mhz includes the 12nh inductive degenera- tion from the lna source to ground. the impedance at 434mhz includes a 10nh inductive degeneration connected from the lna source to ground. the equivalent input circuit is 50 in series with ~2.2pf. the voltage conversion is measured with the lna input-matching inductor, the degeneration inductor, and the lna/mixer tank in place, and does not include the if filter insertion loss. typical operating characteristics ( typical application circuit , v pavdd = v avdd = v dvdd = v hvin = +3.0v, f rf = 433.92mhz, if bw = 280khz, 4kbps manchester encod- ed, 0.2% ber, t a = +25?, unless otherwise noted.) supply current vs. supply voltage max7030 toc01 supply voltage (v) supply current (ma) 3.3 3.0 2.7 2.4 5.8 6.0 6.2 6.4 6.6 6.8 7.0 5.6 2.1 3.6 +85 c +125 c +25 c -40 c supply current vs. rf frequency max7030 toc02 rf frequency (mhz) supply current (ma) 425 400 325 350 375 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.0 300 450 +85 c +125 c +25 c -40 c deep-sleep current vs. temperature max7030 toc03 temperature ( c) deep-sleep current ( a) 110 85 35 60 -10 -15 2 4 6 8 10 12 14 16 18 0 -40 v cc = +3.6v v cc = +3.0v v cc = +2.1v receiver parameter symbol conditions min typ max units crystal oscillator crystal frequency f xtal (f rf -10.7) /24 mhz frequency pulling by v dd 2 ppm/v crystal load capacitance (note 7) 4.5 pf
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 6 bit-error rate vs. average input power max7030 toc04 average input power (dbm) bit-error rate (%) -113 -115 -117 -119 0.1 1 10 100 0.01 -121 -111 f rf = 434mhz f rf = 315mhz 0.2% ber sensitivity vs. temperature temperature ( c) sensitivity (dbm) 110 85 60 35 10 -15 -117 -114 -111 -108 -105 -102 -120 -40 max7030 toc05 f rf = 434mhz f rf = 315mhz rssi vs. rf input power max7030 toc06 rf input power (dbm) rssi (v) -10 -30 -70 -50 -90 -110 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 -130 10 low-gain mode high-gain mode agc switch point agc hysteresis: 3db rssi and delta vs. if input power max7030 toc07 if input power (dbm) rssi (v) -10 -30 -50 -70 0.3 0.6 0.9 1.2 1.5 1.8 2.1 0 -90 10 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 -3.5 delta (%) rssi delta system gain vs. if frequency max7030 toc08 if frequency (mhz) system gain (dbm) 25 20 15 10 5 -10 0 10 20 30 40 50 -20 030 lower sideband upper sideband from rfin to mixout f rf = 434mhz 48db image rejection image rejection vs. temperature max7030 toc09 temperature ( c) image rejection (db) 110 85 60 35 10 -15 44 46 48 42 -40 f rf = 433mhz f rf = 315mhz s11 smith plot of r fin max7030 toc12 433mhz 500mhz 400mhz normalized if gain vs. if frequency max7030 toc10 if frequency (mhz) normalized if gain (db) 10 -16 -12 -8 -4 0 -20 1 100 s11 vs. rf frequency max7030 toc11 rf frequency (mhz) s11 (db) 450 400 350 300 250 -18 -12 -6 0 -24 200 500 433.92mhz typical operating characteristics (continued) ( typical application circuit , v pavdd = v avdd = v dvdd = v hvin = +3.0v, f rf = 433.92mhz, if bw = 280khz, 4kbps manchester encod- ed, 0.2% ber, t a = +25?, unless otherwise noted.) receiver
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 7 input impedance vs. inductive degeneration max7030 toc14 inductive degeneration (nh) real impedance ( ) 10 30 40 50 60 70 80 90 20 imaginary impedance ( ) -210 -200 -190 -180 -170 -160 -150 -220 1 100 f rf = 434mhz imaginary impedance real impedance phase noise vs. offset frequency max7030 toc15 offset frequency (hz) phase noise (dbc/hz) 1m 100k 10k 1k -110 -100 -90 -80 -70 -60 -50 -120 100 10m f rf = 315mhz phase noise vs. offset frequency max7030 toc16 offset frequency (hz) phase noise (dbc/hz) -110 -100 -90 -80 -70 -60 -50 -120 f rf = 433mhz 1m 100k 10k 1k 100 10m typical operating characteristics (continued) ( typical application circuit , v pavdd = v avdd = v dvdd = v hvin = +3.0v, f rf = 433.92mhz, if bw = 280khz, 4kbps manchester encod- ed, 0.2% ber, t a = +25?, unless otherwise noted.) receiver input impedance vs. inductive degeneration max7030 toc13 inductive degeneration (nh) real impedance ( ) 10 30 40 50 60 70 80 90 20 imaginary impedance ( ) -280 -270 -260 -250 -240 -230 -220 -290 1 100 f rf = 315mhz imaginary impedance real impedance
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 8 typical operating characteristics (continued) ( typical application circuit , v pavdd = v avdd = v dvdd = v hvin = +3.0v, f rf = 433.92mhz, if bw = 280khz, 4kbps manchester encod- ed, 0.2% ber, t a = +25?, unless otherwise noted.) supply current vs. supply voltage max7030 toc17 supply voltage (v) supply current (ma) 3.3 3.0 2.7 2.4 10 12 14 16 8 2.1 3.6 f rf = 315mhz pa on without envelope shaping t a = +85 c t a = +125 c t a = -40 c t a = +25 c supply current (ma) 2.5 3.0 3.5 4.0 5.0 4.5 5.5 6.0 2.0 supply current vs. supply voltage max7030 toc18 supply voltage (v) 3.3 3.0 2.7 2.4 2.1 3.6 f rf = 315mhz pa off t a = +85 c t a = +125 c t a = -40 c t a = +25 c supply current vs. supply voltage max7030 toc19 supply voltage (v) supply current (ma) 3.3 3.0 2.7 2.4 11 13 15 17 9 2.1 3.6 f rf = 434mhz pa on without envelope shaping t a = +85 c t a = +125 c t a = -40 c t a = +25 c supply current (ma) 3.0 3.5 4.0 5.0 4.5 5.5 6.0 supply current vs. supply voltage max7030 toc20 supply voltage (v) 3.3 3.0 2.7 2.4 2.1 3.6 f rf = 434mhz pa off t a = +85 c t a = +125 c t a = -40 c t a = +25 c supply current vs. output power average output power (dbm) 6 2 -10 -6 -2 5 6 7 8 9 10 11 12 4 -14 10 max7030 toc21 supply current (ma) f rf = 315mhz pa on envelope shaping enabled pa on 50% duty cycle supply current vs. output power average output power (dbm) 6 2 -10 -6 -2 5 6 7 8 9 10 11 12 13 14 -14 10 max7030 toc22 supply current (ma) f rf = 434mhz pa on envelope shaping enabled pa on 50% duty cycle supply current and output power vs. external resistor max7030 toc23-1 external resistor ( ) supply current (ma) 1k 100 1 10 4 6 8 10 12 14 16 18 2 0.1 10k -12 -8 -4 0 4 8 12 16 -16 output power (dbm) f rf = 315mhz pa on power current supply current and output power vs. external resistor max7030 toc23-2 external resistor ( ) supply current (ma) 1k 100 1 10 4 6 8 10 12 14 16 18 2 0.1 10k -12 -8 -4 0 4 8 12 16 -16 output power (dbm) f rf = 433mhz pa on power current transmitter
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 9 output power vs. supply voltage max7030 24-1 supply voltage (v) output power (dbm) 3.3 3.0 2.7 2.4 6 8 10 12 14 4 2.1 3.6 f rf = 315mhz pa on envelope shaping disabled t a = -40 c t a = +25 c t a = +125 c t a = +85 c output power vs. supply voltage max7030 24-2 supply voltage (v) output power (dbm) 3.3 3.0 2.7 2.4 6 8 10 12 14 4 2.1 3.6 f rf = 315mhz pa on envelope shaping enabled t a = +125 c t a = +25 c t a = -40 c t a = +85 c output power vs. supply voltage max7030 25-1 supply voltage (v) output power (dbm) 3.3 3.0 2.7 2.4 6 8 10 12 14 4 2.1 3.6 f rf = 434mhz pa on envelope shaping disabled t a = +85 c t a = +125 c t a = +25 c t a = -40 c output power vs. supply voltage max7030 25-2 supply voltage (v) output power (dbm) 3.3 3.0 2.7 2.4 6 8 10 12 14 2.1 3.6 f rf = 434mhz pa on envelope shaping enabled t a = +85 c t a = +125 c t a = +25 c t a = -40 c efficiency vs. supply voltage max7030 toc26 supply voltage (v) efficiency (%) 3.3 3.0 2.7 2.4 25 30 35 40 20 2.1 3.6 t a = +85 c t a = +125 c t a = +25 c t a = -40 c f rf = 315mhz pa on efficiency vs. supply voltage max7030 toc27 supply voltage (v) efficiency (%) 3.3 3.0 2.7 2.4 25 30 35 40 20 2.1 3.6 t a = +85 c t a = +125 c t a = +25 c t a = -40 c f rf = 434mhz pa on efficiency vs. supply voltage max7030 toc28 supply voltage (v) efficiency (%) 3.3 3.0 2.7 2.4 15 20 25 30 10 2.1 3.6 t a = +85 c t a = +125 c t a = +25 c t a = -40 c f rf = 315mhz 50% duty cycle efficiency vs. supply voltage max7030 toc29 supply voltage (v) efficiency (%) 3.3 3.0 2.7 2.4 20 25 30 15 2.1 3.6 t a = +85 c t a = +125 c t a = +25 c t a = -40 c f rf = 434mhz 50% duty cycle phase noise vs. offset frequency max7030 toc30 offset frequency (hz) phase noise (dbc/hz) 1m 100k 10k 1k -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -140 100 10m f rf = 315mhz typical operating characteristics (continued) ( typical application circuit , v pavdd = v avdd = v dvdd = v hvin = +3.0v, f rf = 433.92mhz, if bw = 280khz, 4kbps manchester encoded, 0.2% ber, t a = +25?, unless otherwise noted.) transmitter
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 10 phase noise vs. offset frequency max7030 toc31 offset frequency (hz) phase noise (dbc/hz) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -140 f rf = 434mhz 1m 100k 10k 1k 100 10m reference spur magnitude vs. supply voltage max7030 toc32 supply voltage (v) reference spur magnitude (dbc) 3.3 3.0 2.7 2.4 -65 -60 -55 -50 -45 -40 -70 2.1 3.6 434mhz 315mhz -8 -6 -4 -2 0 2 4 6 8 10 -10 frequency stability vs. supply voltage max7030 toc33 supply voltage (v) frequency stability (ppm) 3.3 3.0 2.7 2.4 2.1 3.6 f rf = 434mhz f rf = 315mhz typical operating characteristics (continued) ( typical application circuit , v pavdd = v avdd = v dvdd = v hvin = +3.0v, f rf = 433.92mhz, if bw = 280khz, 4kbps manchester encod- ed, 0.2% ber, t a = +25?, unless otherwise noted.) transmitter
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 11 pin description pin name function 1 pavdd power-amplifier supply voltage. bypass to gnd with 0.01? and 220pf capacitors placed as close as possible to the pin. 2 rout envelope-shaping output. rout controls the power-amplifier envelope? rise and fall times. connect rout to the pa pullup inductor or optional power-adjust resistor. bypass the inductor to gnd as close as possible to the inductor with 680pf and 220pf capacitors, as shown in the typical application circuit . 3 tx/rx1 transmit/receive switch throw. drive t/ r high to short tx/rx1 to tx/rx2. drive t/ r low to disconnect tx/rx1 from tx/rx2. functionally identical to tx/rx2. 4 tx/rx2 transmit/receive switch pole. typically connected to ground. see the typical application circuit . 5 paout power-amplifier output. requires a pullup inductor to the supply voltage (or rout if envelope shaping is desired), which can be part of the output-matching network to an antenna. 6 avdd analog power-supply voltage. avdd is connected to an on-chip +3.0v regulator in 5v operation. bypass avdd to gnd with a 0.1? and 220pf capacitor placed as close as possible to the pin. 7 lnain low-noise amplifier input. must be ac-coupled. 8 lnasrc low-noise amplifier source for external inductive degeneration. connect an inductor to gnd to set the lna input impedance. 9 lnaout low-noise amplifier output. must be connected to avdd through a parallel lc tank filter. ac-couple to mixin+. 10 mixin+ noninverting mixer input. must be ac-coupled to the lna output. 11 mixin- inverting mixer input. bypass to avdd with a capacitor as close as possible to the lna lc tank filter. 12 mixout 330 mixer output. connect to the input of the 10.7mhz filter. 13 ifin- inverting 330 if limiter-amplifier input. bypass to gnd with a capacitor. 14 ifin+ noninverting 330 if limiter-amplifier input. connect to the output of the 10.7mhz if filter. 15 pdmin minimum-level peak detector for demodulator output 16 pdmax maximum-level peak detector for demodulator output 17 ds- inverting data slicer input 18 ds+ noninverting data slicer input 19 op+ noninverting op-amp input for the sallen-key data filter 20 df data-filter feedback node. input for the feedback capacitor of the sallen-key data filter. 21, 25 n.c. no connection. do not connect to this pin. 22 t/ r transmit/ receive . drive high to put the device in transmit mode. drive low or leave unconnected to put the device in receive mode. it is internally pulled down. 23 enable enable. drive high for normal operation. drive low or leave unconnected to put the device into shut- down mode. 24 data receiver data output/transmitter data input 26 dvdd digital power-supply voltage. bypass to gnd with a 0.01? and 220pf capacitor placed as close as possible to the pin. 27 hvin high-voltage supply input. for 3v operation, connect hvin to avdd, dvdd, and pavdd. for 5v operation, connect only hvin to 5v. bypass hvin to gnd with a 0.01? and 220pf capacitor placed as close as possible to the pin.
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 12 detailed description the max7030 315mhz and 433.92mhz cmos trans- ceiver and a few external components provide a com- plete transmit and receive chain from the antenna to the digital data interface. this device is designed for transmitting and receiving ask data. all transmit fre- quencies are generated by a fractional-n-based syn- thesizer, allowing for very fine frequency steps in increments of f xtal /4096. the receive lo is generated by a traditional integer-n-based synthesizer. depending on component selection, data rates as high as 33kbps (manchester encoded) or 66kbps (nrz encoded) can be achieved. receiver low-noise amplifier (lna) the lna is a cascode amplifier with off-chip inductive degeneration that achieves approximately 30db of volt- age gain that is dependent on both the antenna-match- ing network at the lna input and the lc tank network between the lna output and the mixer inputs. the off-chip inductive degeneration is achieved by connecting an inductor from lnasrc to gnd. this inductor sets the real part of the input impedance at lnain, allowing for a more flexible match for low-input impedances such as a pcb trace antenna. a nominal value for this inductor with a 50 input impedance is 12nh at 315mhz and 10nh at 434mhz, but the induc- tance is affected by pcb trace length. lnasrc can be shorted to ground to increase sensitivity by approxi- mately 1db, but the input match must then be reopti- mized. the lc tank filter connected to lnaout consists of l5 and c9 (see the typical application circuit ). select l5 and c9 to resonate at the desired rf input frequency. the resonant frequency is given by: where l total = l5 + l parasitics and c total = c9 + c parasitics . l parasitics and c parasitics include inductance and capacitance of the pcb traces, package pins, mixer- input impedance, lna-output impedance, etc. these parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center fre- quency. lab experimentation should be done to opti- mize the center frequency of the tank. the total parasitic capacitance is generally between 5pf and 7pf. automatic gain control (agc) when the agc is enabled, it monitors the rssi output. when the rssi output reaches 1.28v, which corre- sponds to an rf input level of approximately -55dbm, the agc switches on the lna gain-reduction attenua- tor. the attenuator reduces the lna gain by 36db, thereby reducing the rssi output by about 540mv to 740mv. the lna resumes high-gain mode when the rssi output level drops back below 680mv (approxi- mately -59dbm at the rf input) for a programmable interval called the agc dwell time (see table 1). the agc has a hysteresis of approximately 4db. with the agc function, the rssi dynamic range is increased, allowing the max7030 to reliably produce an ask out- put for rf input levels up to 0dbm with a modulation depth of 18db. agc is not required and can be dis- abled (see table 1). f lc total total = 1 2 pin description (continued) pin name function 28 agc2 agc enable/dwell time control 2 (msb). see table 1. bypass to gnd with a 10pf capacitor. 29 agc1 agc enable/dwell time control 1. see table 1. bypass to gnd with a 10pf capacitor. 30 agc0 agc enable/dwell time control 0 (lsb). see table 1. bypass to gnd with a 10pf capacitor. 31 xtal1 crystal input 1. bypass to gnd if xtal2 is driven by an ac-coupled external reference. 32 xtal2 crystal input 2. xtal2 can be driven from an external ac-coupled reference. ep exposed pad. solder evenly to the board? ground plane for proper operation.
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 13 agc dwell-time settings the agc dwell timer holds the agc in low-gain state for a set amount of time after the power level drops below the agc switching threshold. after that set amount of time, if the power level is still below the agc threshold, the lna goes into high-gain state. this is important for ask since the modulated data may have a high level above the threshold and low level below the threshold, which without the dwell timer would cause the agc to switch on every bit. the max7030 uses the three agc control pins (agc0, agc1, agc2) to set seven user-controlled, dwell-timer settings. the agc dwell time is dependent on the crys- tal frequency and the bit settings of the agc control pins. to calculate the dwell time, use the following equation: where k is an odd integer in decimal from 11 to 23, deter- mined by the control pin settings shown in table 1. to calculate the value of k, use the following equation and use the next integer higher than the calculated result: k 3.3 x log 10 (dwell time x f xtal ) for manchester code (50% duty cycle), set the dwell time to at least twice the bit period. for nonreturn-to- zero (nrz) data, set the dwell to greater than the peri- od of the longest string of zeros or ones. for example, using manchester code at 315mhz (f xtal = 12.679mhz) with a data rate of 2kbps (bit period = 250?), the dwell time needs to be greater than 500?: k 3.3 x log 10 (500? x 12.679) 12.546 choose the agc pin settings for k to be the next odd- integer value higher than 12.546, which is 13. this says that agc1 is set high and agc0 and agc2 are set low. mixer a unique feature of the max7030 is the integrated image rejection of the mixer. this eliminates the need for a costly front-end saw filter for many applications. the advantage of not using a saw filter is increased sensitivity, simplified antenna matching, less board space, and lower cost. the mixer cell is a pair of double-balanced mixers that perform an iq downconversion of the rf input to the 10.7mhz intermediate frequency (if) with low-side injection (i.e., f lo = f rf - f if ). the image-rejection circuit then combines these signals to achieve a typical 46db of image rejection over the full temperature range. low- side injection is required as high-side injection is not possible due to the on-chip image rejection. the if out- put is driven by a source follower, biased to create a driving impedance of 330 to interface with an off-chip 330 ceramic if filter. the voltage-conversion gain dri- ving a 330 load is approximately 20db. note that the mixin+ and mixin- inputs are functionally identical. integer-n phase-locked loop (pll) the max7030 utilizes a fixed-integer-n pll to generate the receive lo. all pll components, including the loop filter, voltage-controlled oscillator, charge pump, asyn- chronous 24x divider, and phase-frequency detector are integrated internally. the loop bandwidth is approx- imately 500khz. the relationship between rf, if, and crystal reference frequencies is given by: f xtal = (f rf - f if )/24 dwell time f k xtal = 2 agc2 agc1 agc0 description 0 0 0 agc disabled, high gain selected 001 k = 11 010 k = 13 011 k = 15 100 k = 17 101 k = 19 110 k = 21 111 k = 23 table 1. agc dwell time settings for max7030
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 14 intermediate frequency (if) the if section presents a differential 330 load to pro- vide matching for the off-chip ceramic filter. the internal six ac-coupled limiting amplifiers produce an overall gain of approximately 65db, with a bandpass filter type response centered near the 10.7mhz if frequency with a 3db bandwidth of approximately 10mhz. for ask data, the rssi circuit demodulates the if to baseband by producing a dc output proportional to the log of the if signal level with a slope of approximately 15mv/db. data filter the data filter for the demodulated data is implemented as a 2nd-order, lowpass, sallen-key filter. the pole locations are set by the combination of two on-chip resistors and two external capacitors. adjusting the value of the external capacitors changes the corner fre- quency to optimize for different data rates. set the cor- ner frequency in khz to approximately 3 times the fastest expected manchester data rate in kbps from the transmitter (1.5 times the fastest expected nrz data rate). keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. the configuration shown in figure 1 can create a butterworth or bessel response. the butterworth filter offers a very-flat-amplitude response in the passband and a rolloff rate of 40db/decade for the two-pole filter. the bessel filter has a linear phase response, which works well for filtering digital data. to calculate the value of the capacitors, use the following equations, along with the coefficients in table 2: where f c is the desired 3db corner frequency. for example, choose a butterworth filter response with a corner frequency of 5khz: choosing standard capacitor values changes c f1 to 470pf and c f2 to 220pf. in the typical application circuit , c f1 and c f2 are named c16 and c17, respectively. data slicer the data slicer takes the analog output of the data filter and converts it to a digital signal. this is achieved by using a comparator and comparing the analog input to a threshold voltage. the threshold voltage is set by the voltage on the ds- pin, which is connected to the nega- tive input of the data slicer comparator. numerous configurations can be used to generate the data-slicer threshold. for example, the circuit in figure 2 shows a simple method using only one resistor and one capacitor. this configuration averages the analog output of the filter and sets the threshold to approxi- mately 50% of that amplitude. with this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. the values of r and c affect how fast the thresh- old tracks the analog amplitude. be sure to keep the corner frequency of the rc circuit much lower (about 10 times) than the lowest expected data rate. with this configuration, a long string of nrz zeros or ones can cause the threshold to drift. this configuration works best if a coding scheme, such as manchester coding, which has an equal number of zeros and ones, is used. figure 3 shows a configuration that uses the positive and negative peak detectors to generate the threshold. this configuration sets the threshold to the midpoint between a high output and a low output of the data filter. c k khz pf c k khz pf f f 1 2 1 000 1 414 100 3 14 5 450 1 414 4 100 3 14 5 225 = = . ( . )( )( . )( ) . ( )( )( . )( ) c b ak f c a kf f c f c 1 2 100 4 100 = = ()()() ()()() max7030 rssi 100k c f2 c f1 100k df op+ ds+ figure 1. sallen-key lowpass data filter filter type a b butterworth (q = 0.707) 1.414 1.000 bessel (q = 0.577) 1.3617 0.618 table 2. coefficients to calculate c f1 and c f2
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 15 peak detectors the maximum peak detector (pdmax) and minimum peak detector (pdmin), with resistors and capacitors shown in figure 3, create dc output voltages equal to the high- and low-peak values of the filtered demodulat- ed signal. the resistors provide a path for the capaci- tors to discharge, allowing the peak detectors to dynamically follow peak changes of the data filter out- put voltages. the maximum and minimum peak detectors can be used together to form a data slicer threshold voltage at a value midway between the maximum and minimum voltage levels of the data stream (see the data slicer section and figure 3). set the rc time constant of the peak detector combining network to at least 5 times the data period. if there is an event that causes a significant change in the magnitude of the baseband signal, such as an agc gain-switch or a power-up transient, the peak detectors may ?atch?a false level. if a false peak is detected, the slicing level is incorrect. the max7030 peak detectors correct these problems by temporarily tracking the incoming baseband filter voltage when an agc state switch occurs, or forcing the peak detectors to track the baseband filter output voltage until all internal circuits are stable following an enable pin low-to-high transition and also t/ r pin high-to-low transition. the peak detectors exhibit a fast attack/slow decay response. this feature allows for an extremely fast startup or agc recovery. transmitter power amplifier (pa) the pa of the max7030 is a high-efficiency, open- drain, switch-mode amplifier. the pa with proper output-matching network can drive a wide range of antenna impedances, which includes a small-loop pcb trace and a 50 antenna. the output-matching network for a 50 antenna is shown in the typical application circuit . the output-matching network suppresses the carrier harmonics and transforms the antenna imped- ance to an optimal impedance at paout (pin 5). the optimal impedance at paout is between 100 and 150 to transmit +10dbm with a 2.7v supply. when the output-matching network is properly tuned, the pa transmits power with a high overall efficiency of up to 32%. the efficiency of the pa itself is more than 46%. the output power is set by an external resistor at paout and is also dependent on the external antenna and antenna-matching network at the pa output. envelope shaping the max7030 features an internal envelope-shaping resistor, which connects between the open-drain output of the pa and the power supply (see the typical application circuit ). the envelope-shaping resistor slows the turn-on/turn-off of the pa in ask mode and results in a smaller spectral width of the modulated pa output signal. fractional-n phase-locked loop (pll) the max7030 utilizes a fully integrated, fractional-n, pll for its transmit frequency synthesizer. all pll com- ponents, including the loop filter, are integrated inter- nally. the loop bandwidth is approximately 200khz. power-supply connections the max7030 can be powered from a 2.1v to 3.6v sup- ply or a 4.5v to 5.5v supply. if a 4.5v to 5.5v supply is used, then the on-chip linear regulator reduces the 5v supply to the 3v needed to operate the chip. to operate the max7030 from a 3v supply, connect pavdd, avdd, dvdd, and hvin to the 3v supply. when using a 5v supply, connect the supply to hvin max7030 c pdmax pdmin r c r data slicer data peak det peak det figure 3. generating data-slicer threshold using the peak detectors max7030 c ds- ds+ r data slicer data figure 2. generating data-slicer threshold using a lowpass filter
only and connect avdd, pavdd, and dvdd together. in both cases, bypass dvdd, hvin, and pavdd to gnd with 0.01? and 220pf capacitors and bypass avdd to gnd with 0.1? and 220pf capacitors. bypass t/ r , enable, data, and agc0-2 with 10pf capacitors to gnd. place all bypass capacitors as close as possible to the respective pins. transmit/ receive antenna switch the max7030 features an internal spst rf switch that, when combined with a few external components, allows the transmit and receive pins to share a common antenna (see the typical application circuit) . in receive mode, the switch is open and the power amplifier is shut down, presenting a high impedance to minimize the loading of the lna. in transmit mode, the switch closes to complete a resonant tank circuit at the pa output and forms an rf short at the input to the lna. in this mode, the external passive components couple the output of the pa to the antenna and protect the lna input from strong transmitted signals. the switch state is controlled by the t/ r pin (pin 22). drive t/ r high to put the device in transmit mode; drive t/ r low to put the device in receive mode. control interface considerations when operating the max7030 with a +4.5v to +5.5v supply voltage, the agc0, acg1, agc2, data, enable and t/ r pins may be driven by a microcon- troller with either 3v or 5v interface logic levels. when operating the max7030 with a +2.1v to +3.6v supply, the microcontroller must produce logic levels which conform to the v ih and v il specifications in the dc electrical characteristics for the max7030. crystal oscillator (xtal) the xtal oscillator in the max7030 is designed to pre- sent a capacitance of approximately 3pf between the xtal1 and xtal2 pins. in most cases, this corre- sponds to a 4.5pf load capacitance applied to the external crystal when typical pcb parasitics are added. it is very important to use a crystal with a load capacitance that is equal to the capacitance of the max7030 crystal oscillator plus pcb parasitics . if a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. crystals designed to operate with higher differential load capacitance always pull the ref- erence frequency higher. in actuality, the oscillator pulls every crystal. the crys- tal? natural frequency is really below its specified fre- quency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. this pulling is already accounted for in the specification of the load capacitance. additional pulling can be calculated if the electrical parameters of the crystal are known. the frequency pulling is given by: where: f p is the amount the crystal frequency is pulled in ppm. c m is the motional capacitance of the crystal. c case is the case capacitance. c spec is the specified load capacitance. c load is the actual load capacitance. when the crystal is loaded as specified, i.e., c load = c spec , the frequency pulling equals zero. f c cc cc x p m case load case spec = + ? + ? ? ? ? ? ? 2 11 10 6 max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 16 32 31 30 29 28 27 26 9 10 11 12 13 14 15 18 19 20 21 22 23 24 7 6 5 4 3 2 1 max7030 thin qfn top view rout pavdd tx/rx1 tx/rx2 paout avdd lnain 8 lnasrc xtal2 xtal1 agc0 agc1 agc2 hvin dvdd 25 + n.c. data enable t/r n.c. df op+ ds+ 17 ds- pdmin ifin+ 16 pdmax ifin- mixout mixin- mixin+ lnaout pin configuration
max7030 component value for 433.92mhz rf value for 315mhz rf description c1 220pf 220pf 5% c2 680pf 680pf 5% c3 6.8pf 12pf 5% c4 6.8pf 10pf 5% c5 10pf 22pf 5% c6 220pf 220pf 5% c7 0.1f 0.1f 10% c8 100pf 100pf 5% c9 1.8pf 2.7pf 0.1pf c10 100pf 100pf 5% c11 220pf 220pf 5% c12 100pf 100pf 5% c13 1500pf 1500pf 10% c14 0.047f 0.047f 10% c15 0.047f 0.047f 10% c16 470pf 470pf 5% c17 220pf 220pf 5% c18 220pf 220pf 5% c19 0.01f 0.01f 5% c20 100pf 100pf 5% c21 100pf 100pf 5% c22 220pf 220pf 5% c23 0.01f 0.01f 10% c24 0.01f 0.01f 10% l1 22nh 27nh 5% or better* l2 22nh 30nh 5% or better* l3 22nh 30nh 5% or better* l4 10nh 12nh 5% or better* l5 16nh 30nh 5% or better* l6 68nh 100nh 5% or better* r1 100k 100k 5% r2 100k 100k 5% r3 0 0 x1 17.63416mhz 12.67917mhz crystal, 4.5pf c load , crystek or hong kong crystal y1 10.7mhz ceramic filter 10.7mhz ceramic filter murata table 3. component values for typical application circuit low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 17 * wire wound recommended. note: component values vary depending on pcb layout.
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 18 1 2 3 4 5 6 7 8 c8 l3 c6 910 11 c10 c12 c9 12 l5 c11 13 in out gnd 14 15 16 y1 c13 17 18 19 20 21 22 23 24 c17 r1 25 26 27 28 29 30 32 31 agc1 agc0 max7030 3.0v c23 v dd v dd pavdd rout tx/rx1 tx/rx2 paout avdd lnain lnasrc lnaout mixin+ mixin- ifin+ ifin- pdmin pdmax mixout ds- ds+ op+ df n.c. t/r enable data n.c. dvdd hvin agc2 agc1 agc0 xtal1 xtal2 agc2 c20 c21 x1 l4 c14 c15 data enable c16 transmit/ receive c22 c5 c4 c18 c19 c7 l1 l2 c1 c2 r2 r3* *optional power-adjust resistor c24 exposed pad c3 l6 v dd v dd v dd typical application circuit chip information process: cmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 32 thin qfn-ep t3255+3 21-0140 90-0001
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll 19 lna 90 0 rssi if limiting amps 100k 100k data filter 7 8 9 10 11 12 14 13 20 19 rx data 18 15 16 17 30 29 28 24 23 22 digital logic 31 32 crystal oscillator 27 3.0v regulator 6 26 pa max7030 5 1 2 rx vco rx frequency divider phase detector charge pump loop filter tx frequency divider i q tx vco ? modulator exposed pad lnain lnasrc tx/rx1 tx/rx2 xtal1 xtal2 hvin avdd rout pavdd paout t/r dvdd enable data agc2 agc1 agc0 ds- pdmax pdmin ds+ op+ df ifin+ ifin- mixout mixin- mixin+ lnaout 3 4 functional diagram
max7030 low-cost, 315mhz and 433.92mhz ask transceiver with fractional-n pll maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical. characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidan ce. 20 ____________________maxim integrated products, 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 5/05 initial release 1 9/08 added + to each part to denote lead-free/rohs-compliant package and explicitly calling out the odd frequency as contact factory for availability 1 2 6/09 made correction in power amplifier (pa) section 15 3 11/10 updated ac electrical characteristics, absolute maximum ratings, and package information 2, 5, 18 4 6/12 deleted the max7030matj+ from the selector guide and all references to the max7030matj+ throughout the data sheet; updated f xtal reference in the phase- locked loop section; updated power amplifier section; inserted control interface considerations ; updated table 3 1, 13, 15, 16, 17, 18

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